The present application relates to a memory architecture comprising a plurality of memory banks or a plurality of memory devices for storing information units and a memory controller, in particular to a memory architecture according to DRAM technology.
High speed memories are a critical resource in system performance like network systems, graphic controllers, CPU architectures, etc. Architectures like caching are a common approach when the access pattern is not completely random. However, in applications like switches, routers and other types of network devices this is not the case. The memory access pattern is derived from the packet arrival which is completely random.
The DRAM (dynamic random access memory) technology has poor performance for applications with random access nature. The barrier lies in the memory intrinsic delay when switching from one row to another in the same bank. This delay is known as tRC (row cycle time) and its magnitude remained almost unchanged since the very first DRAM devices until today. The limitations of DRAM memories in networking applications are mainly the random access rate and not the bandwidth. There are limiting factors like tRRD (row active to row active delay) and tFAW (four band activation window time) that reduce memory performance significantly under random access scenarios. However, despite this performance bottleneck there are other advantages that make DRAM technology irreplaceable. The advantages are very high density, low cost and low power. In applications that demand both, high density and high performance, alternatives like SRAM (static random access memory) technology are impractical to use due to cost, power and area issues. So it is desired to improve the performance of the DRAM technology in order to open new opportunities in fields such as network communication and similar applications that require high rates of short random accesses for storing different types of information units, such as packet descriptors or control packets, statistical counters, but also data packets in network communication.